M8: the daisy chain, once 5V reached the second drive
My board and the working UniDisk now sit on one Liron card in either order, and ProDOS sees both drives. Copy II Plus copied /M7TEST from my drive to the UniDisk, all 1600 blocks, and the sentinel boots from the copy with all four checksums. The bench supply is gone too, and the Pico now runs off the IIe’s +5, so the IIe’s power switch runs the whole rig.
Off the bench supply first
I wanted the bench supply gone before the chain. The rear port passes the IIe’s rails straight through to the next drive, and I didn’t want a UniDisk on the Apple’s +5 while my board ran on the bench’s.
J1.11 now feeds the board’s +5 net and J1.13 and J1.15 feed +12 to the mechanism. The sentinel boot and SPCOMPARE gave the same results as on the bench supply.
| Rail | At the board |
|---|---|
| +5 | 4.54 V |
| +12 | 12.2 V |
4.54 V is under the Sony spec’s 4.75 V. Reads passed, so I left it. That came back later.
The rear port is mostly copper
I beeped a dead IF-83 from the rear DB-19 to the host connector. 16 of the 19 pins are straight through. The other three go to the gate array:
| DB-19 pin | Signal | What the drive does with it |
|---|---|---|
| 14 | PH3 out | copies PH3 once it has its ID |
| 16 | LASTONE/ | senses it through a 2k pull-up |
| 17 | /ENBL out | copies /ENBL once it has its ID |
Pin 16 on the host side is grounded on the drive. So every drive pulls pin 16 low toward the drive in front of it, and reads its own rear pin 16 to see if anything is behind it. Low means another drive, high means it’s last.
My rear port is an IDC40 breakout using positions 1-20, a ribbon crimped flat, and a DB-19 soldered wire by wire in Apple’s mapping, every pin heat-shrunk. A loopback command on the Pico drove PH3_OUT and ENBL_OUT through the rear port and a cable back into the host inputs. Both followed, and nothing else moved. The pass-through pins I beeped end to end from DB-19 to DB-19.
Pass-through is one PIO instruction
The drive ROM sets its PH3 enable once every drive inside it has an ID, and only a reset clears it. I did the same. The first INIT while I have no ID is mine. I read LASTONE/, answer last or not-last, and switch on the pass-through before my reply goes out. Any INIT after that is for the drive behind me, and I don’t ACK it.
The pass-through is mov pins, pins on two state machines in the third PIO block. One copies host PH3 to PH3_OUT, the other host /ENBL to ENBL_OUT. A bus reset hands both pins back to plain GPIO at their idle levels.
My old reply landed on top of the UniDisk’s
The first chained boot looked right. LASTONE/ read 0, I took ID 1 and the UniDisk took ID 2. Bitsy Bye still skipped S5,D2. The board log showed it:
SPL IGN d=2 c=01 b=2 s=00
SPL REREAD
After a READBLOCK for ID 2, the card raises REQ to read the UniDisk’s reply. My firmware saw REQ high with no write and a reply still saved, and took it as the card asking for my last reply again. That’s the re-read path from M7, and with one drive it’s right. With two, I was talking over the UniDisk. Now any command packet that isn’t mine throws the saved reply away, and a checksum failure does the same since that packet might have been for the other drive.
The UniDisk was starving at 4.3 V
With that fixed, S5,D2 listed, but it took minutes. The card sent READBLOCK 2 to ID 2 about 6000 times in a row before one went through. The UniDisk’s light stayed on from boot, its motor never stopped, and its eject button did nothing.
Swapping the order, UniDisk on the card and my board behind it, made both drives quick. I took ID 2 and answered last. So the trouble only showed with the UniDisk at the back.
The scope cleared the pass-through. PH3_OUT sat at 4.2 to 4.4 V the whole time and the card’s packets reached the UniDisk, which just never ACKed. The meter found it:
| Where | +5 |
|---|---|
| IIe slot | 5.34 V |
| Rear port J3.11, UniDisk spinning | 4.3 V |
| Same, some cards pulled | 4.55 V |
| Same, 24 AWG on the +5 run | 4.7 V |
The IIe was fine. Nearly a volt went in my wiring, mostly in the thin jumpers on the +5 path. The drive at the end of the chain draws its whole supply through every wire in front of it, so it gets hit hardest. With 24 AWG, S5,D2 answers straight away.
If a UniDisk chained behind another drive spins with its light on and takes minutes to list, meter +5 at its DB-19 pin 6 while it’s spinning. Under about 4.75 V the mechanism can’t read.
A whole disk through the chain
Copy II Plus copied my D1 (/M7TEST) onto the UniDisk in D2, over a REF800K disk, with no errors. D2 catalogs as /M7TEST, 1511 blocks used. Then the sentinel booted from the UniDisk’s copy, so every byte my board read went through the pass-through, onto the UniDisk’s disk, and back.
The front eject button is wired now: a plain switch from GP22 to ground, using the Pico’s internal pull-up. Press and release, and the disk comes out.
The Pico on the IIe’s 5V
The last cord was the Pico’s USB. Board +5 now feeds the Pico’s VSYS pin through a small diode, band toward VSYS. Without it, USB plugged in later for the console would feed 5 V from VSYS back into the IIe’s rail with the Apple switched off. With USB unplugged and the IIe on, the Pico came up with it, the sentinel booted from my drive and S5,D2 listed on the UniDisk.
Open threads
- 4.7 V is still under the 4.75 V spec. The PCB needs wide +5, +12 and GND traces from the host connector to the rear DB-19, as well as to the mechanism.
- The board counters show 5 timeouts and 5 re-reads for the session. Most of the session ran starved, so I want a clean boot with the 24 AWG in place to see if they come back.
- Still to run on IIe power: a full-disk read scan, and SPCOMPARE with the disk write-protected and with the drive empty.
- The Pico and the mechanism now power up and down together. In M0 each Pico power edge put a short strobe on LSTRB, so that’s worth a look on the scope at IIe power-on and power-off.
- M9 is robustness: swapping disks mid-session, write-protected and empty drives, long copy loops.