M6: the Liron's first packet reaches my board

The host side of my board is back on the Apple, and it’s safe this time. The Liron card’s reset pulse and its first SmartPort command packet show up on the Pico’s inputs, and the packet decodes on the scope: sync, then C3 for packet begin. There’s no SmartPort firmware yet, so the IIe still says no device connected.

The breakouts have the rails on their own row

The homemade DB-19 adapter that put -12 V on /WRREQ is gone. I got two KingPow IDC20P-B boards, 2x10 IDC to screw terminals with a DIN rail mount. One is J1 for the host side. The other goes on the mechanism side, because my CN104 tap had the same problems.

My DB-19 to IDC20 cable is wired like the cable inside a UniDisk. DB-19 pin n goes to flat pin 2n-1 for pins 1 to 9, pins 11 to 19 go to the even side, and ACK (DB-19 pin 10) goes to flat pin 20. Flat 19 has no wire. I had ACK on 19 in my notes from the old adapter and caught it before wiring.

That interleave puts GND and every Apple rail on the odd row of terminals and the signals on the even row. The -12 V is on J1.9 and /WRREQ is on J1.10, a whole terminal row apart. My board runs off the bench supply, so the rail terminals stay empty.

Before any power I beeped every signal from the DB-19 pin to its shifter pin, then every Apple rail against every other pin, the bench +5 and the 3.3 V rail. Everything that should connect beeped and nothing else did.

The bench supply can’t read small currents

On the first power-up the bench +5 went into current limit at 10 mA and sat at 1.43 V. The mechanism was still hanging off the bench +5 through the old CN104 tap, and its logic draws tens of mA on +5 alone. I unplugged it.

With the mechanism off, the supply still showed 30 mA. A DMM in series with each shifter’s VCCB read 0.04 mA per board, so the supply’s readout is just off at that end. Its 0.01 A limit also kicks in well under 10 mA. For anything this small I use the DMM now, and 0.05 A is the lowest limit I trust.

First connect, Pico unplugged

With the Pico unplugged both shifters sit in Hi-Z, so this checks the rails and idle levels with nothing of mine driving. The current stayed at 0.04 mA when the IIe came on.

/WRREQ and /HSTEN read 5.15 V because the bench was set to 5.15 V and they have 10k pull-ups to it. I dropped the bench to 5.00 V. U3 drives RD and ACK at its VCCB, and that shouldn’t sit 0.4 V above the 4.73 V the Liron runs on.

Reading the host lines over SWD

Next the Pico went on with the M5 firmware, which holds U3’s /OE high so RD and ACK stay off the bus. I read the GPIO input register over SWD without halting. The first read had PH2 high and PH3 low while J1 showed the opposite. My jumpers were shifted by one at the Pico header. After fixing that the Pico matched J1.

Then I sampled the inputs for 25 s, about 4,000 reads a second, while I typed PR#5:

My pull-up holds ACK high, so the Liron thinks a device is ready and starts sending.

WR idled under the shifter’s threshold

WR measured 3.56 V idle on the meter, and the SN74LVC8T245 only guarantees a high above 0.7 x VCCB, 3.5 V at 5 V. So I put it on the scope during PR#5: /WRREQ, WR and PH0 (REQ), triggered on /WRREQ falling.

During the packet WR swings 0.04 V to 4.36 V, which is fine. Idle it sat at 3.40 V with about 0.25 V of noise, under the threshold. The cause was my own 10k pull-down on U1 B7. I swapped it for a 100k and idle came up to 3.96 V. Working back from the two idle levels, the Liron drives idle WR at about 4.0 V through about 1.9k, so 4.0 V is as high as it goes.

If you’re level-shifting a Liron card’s WR with an LVC8T245 at 5 V, keep the pull-down weak. The card idles WR at about 4.0 V through about 1.9k, and a 10k pull-down drags it to 3.4 V, under the 3.5 V input-high.

The packet

Zoomed in at 20 us/div, REQ comes up 7.7 us before /WRREQ drops, and the first WR edge is 3.95 us after that. The cells are 3.91 us, which is the IWM’s 7.16 MHz divided by 28. Taking each transition as a 1, the start decodes to:

FF 3F CF F3 FC FF   sync
C3                  packet begin
81                  destination ...

It looked very familiar from the Byte Hamr days. Those sync bytes are also the same self-sync pattern the drive writes as its track preamble, which my board already writes from M5.

Still open

• Put the mechanism side on the second breakout, with short heavy +5 V and GND runs, and check the read scan at 5.0 V.
• Write the M6 spec: the FM receiver, the ACK handshake, and what the RAM disk holds.
• WR has about 0.5 V of margin at idle now. Watch it once the receiver is running.
• Re-format disk 2 with my board.