UniDisk 3.5 controller

hardware / status: active

The UniDisk 3.5 is the only way to get 3.5" disks on an Apple IIe, and when its controller board dies you’re stuck. The Sony gate array on it has no datasheet, and the one spare board on eBay has been sitting at $150 for months. This is a replacement board built around an RP2350 that talks SmartPort to the Apple and drives the Sony mechanism directly.

Current state

As of 2026-10-10: Design is done and written down. The two 20-pin cable breakouts are built and beep-checked. The M0 scaffold firmware builds and passes its host tests. Next is M0 on the bench: Pico 2 and the first two shifter boards wired, mechanism power test, and a scope check that the mechanism lines stay quiet through a reset.

Architecture

One RP2350 replaces the 65C02, ROM, RAM, IWM and the CXD1013 gate array. It talks to the stock Sony 800K mechanism through its 20-pin connector and to the Apple through the DB-19.

Host side: SmartPort over FM in one PIO block, ported from the PicoPort code in the Byte Hamr repo. Core 0 runs the protocol.
Mechanism side: a second PIO block times flux on RD and writes GCR on WRTDATA. Core 1 runs seek, speed zones, a whole-track read buffer and per-sector writes.
Daisy chain: PH3 and /ENBL get passed to the rear port once the drive has its SmartPort ID, and LASTONE (rear pin 16) tells it whether anything is plugged in behind.
The original drive ROM is used as a reference for command handling and timing. The firmware is my own C.

Scope is the Apple IIe with 800K ProDOS disks.

Hardware

Part	What
Raspberry Pi Pico 2 (RP2350A)	Prototype controller. 25 of 26 GPIO used.
SN74LVC8T245 boards x5	3.3 V to 5 V level shifting, one DIR and /OE per 8 channels
74LVC1G07	Open-drain SmartPort ACK
Sony 800K mechanism	CX23077A logic, CX20185 read/write amp, +5 V and +12 V only
Test drives	Two UniDisk 3.5s with dead controllers, one working drive kept stock

The mechanism connector is the Mac 800K drive’s 20-pin header. Pin 20 (/PWM) is tied to +5V, as on the original board.

Gateware and firmware

C on the Pico SDK 2.2.0, built with CMake and Ninja. Loaded and debugged over SWD with a picoprobe, Raspberry Pi’s OpenOCD build and arm-none-eabi-gdb. The mechanism logic and the console parser are unit-tested on the Mac against a fake bus. A Python tool decodes flux captures offline into a disk image. The repo is local for now.

Open problems

Writes: 3.5" GCR has no index pulse, so each write has to catch its sector header on the fly. Write precompensation isn’t in any doc I have.
The /ENBL pass-through rule for the daisy chain is inferred from the ROM and not yet checked.
The byte order inside GCR data groups gets confirmed on the first real capture.