Carved out of the core repo, and the LiteX chain builds again

The Ethernet monitor design spec went into the core repo on 2026-07-09, and the next day I pulled projects/b8008_net out of intel-8008-vhdl at commit 311df3f into a fresh repo called remote_8008. Tracked files only. The vendored LiteX trees and build products get recreated by make litex-env, which pins LiteX 2026.04 into a local venv. The top-level Python moved into soc/, and rom_4kx8_bram.vhdl came across from the monitor project.

The core itself doesn’t get copied. It comes in as the FuseSoC core greygiant:retro:b8008 through its ghdl_synth_verilog generator, with CORE_DIR pointing at the core checkout. This is the same arrangement the Byte Hamr card uses, so the 8008 has one source of truth and two consumers.

Two things broke on the move. soc/versa_soc.py computed the netlist path relative to its own directory instead of the repo-root build/, so make build couldn’t find what make convert had just produced. The same fix had already gone into the bench script. And host/tests/test_selftest.py still looked for host_selftest.py one level above host/, where it sat in the monorepo layout.

The third thing wasn’t the repo. Every RISC-V compile, BIOS and firmware alike, died with “internal compiler error: Abort trap: 6”. otool -L on cc1 showed it couldn’t load libisl.23.dylib or libmpc.3.dylib. brew install isl mpfr fixed it. Homebrew’s riscv-gnu-toolchain had lost its runtime deps and was reporting it as a compiler bug.

A fresh checkout has an ordering problem too. make bootstrap-headers has to run before make firmware, and it can’t be an automatic prerequisite without a circular edge between build and firmware. It’s in the README and a Makefile comment.

After that, make sim-core, make sim-netlist, make sim-bench and make build all pass in the new layout. Nothing has been loaded on the board from this repo yet.