First b8008 silicon, and Yosys eats the ROM

What I tried

On 2026-01-02 the external ROM component became an embedded one, the internal tri-state bus became a mux, and the core went onto the Versa. The TODO from that day records the hardware tests passing and estimated opcode coverage at about 95%. That’s version 2.1.

The next two days were serial. UART TX on 01-03, then RX, then a b8008_usart component with the handshaking the CPU wants, and a UART echo demo on 01-04. The interactive monitor started the same day.

What broke

The ROM. A 4 KB ROM synthesized to garbage on hardware while simulation was fine. On 01-05 I narrowed it: a ROM with (others => x"FF") as the default fill came out corrupted, and the same ROM with x"00" fill came out right. Switching the fill also let the ROM drop to 1 KB. On 01-06 a second variant showed up with file-based ROM initialization, so the build now generates a VHDL ROM with an explicit array initializer straight from the Intel HEX file. Both are Yosys bugs, both worked around, neither understood at the time.

With that out of the way the monitor’s H command worked on 01-07, and D (memory dump) landed the same day.

What else

I posted the project to the VCF forum on 01-08 asking for FPGA advice. One reply pushed back on internal tri-state buses and inferred block RAM. I’d already gone to a mux, and the block RAM point turned out to matter later.

On 01-09 a three-button debug clock controller went in for single-stepping the CPU, plus a hardware breakpoint after bootstrap.

Next

External ROM. An AT28C64B EEPROM like the SIM8-01 used, so the ROM problem goes around Yosys entirely.