The control unit, on a notebook page
Backfilled from a post on embedded.greygiant.com dated 2025-07-18.
What I tried
Nothing on the bench. I’d had counters, a memory interface and a sequencer working on their own for weeks and couldn’t make them into a computer, so I stopped wiring and sat with Malvino’s SAP-1 and a notebook.
SAP-1 runs six timing states, T0 through T5. T0 to T2 are the fetch and are the same for every instruction: PC onto the address bus and memory read, PC increment, load the IR. T3 to T5 are the execute and depend on the opcode. Malvino builds the decoder out of gates. I’m going to do it with an EEPROM: the opcode bits and the timing state bits together form the address, and the byte at that address is the control word for that instruction in that phase. That’s the whole control unit.
The ring counter out of what I had
I wanted a 74LS164 for the ring and didn’t have one. What I did have:
- 74S163, a 4-bit synchronous counter, counts 0 to 5
- 74LS138, turns the count into six one-hot active-low outputs, T0 to T5
- 74LS00, one NAND on QB and QC catches count 6 (binary 110) and pulls the ‘163’s CLR, so it goes straight back to 0
What surprised me
I’d been treating the mode switching as an afterthought. It turned out to be the control unit, and the counters and memory I’d spent weeks on all hang off it.
Next
Map the data paths between SRAM, registers, ALU and output. Enumerate every enable. Put the matrix in a 28C256. Write the control words for SAP-1’s instruction set.