OUT before a RAM fetch halts; the breadboard is done

What I tried

RAM programs were stopping. life.asm printed row 0, OB read 0x01, and the machine froze with no response to keys. bigxfer at 2233 bytes has gone in and streamed itself back clean several times, sometimes back to back, and then a table bump or a wire out of line stops it (one run: monitor sum 0x69 against host 0x29, OB 0xC2, monitor unresponsive). Every earlier RAM program had done five firsts at once, so I wrote a staircase, asm/ram/step1..8, one first per step, with the Python oracle as the answer key.

step2 is LDAI 0x22; OUT; RET. It OUTs 0x22 and freezes. Fetch, OUT, HALT, RET and CALL from RAM all work on their own; only OUT immediately before another instruction fetched from RAM halts. Data-independent: four OUT values all froze, and OUT of 0x34 with REG_A already 0x34, no bus transition, still froze. One instruction between them cures it (step2a). One NOP cures it (step2g, OB 0x22, prompt back). That was NOP’s first execution on silicon.

First model: OUT was one row driving MDR from REG_A and strobing the output latch in the same T-state that carried END, so the next fetch began before the bus released. Fix: a SETTLE row that drives nothing before END. Reburned U15, CRC 0xDCD1 to 0x45F9, one chip.

What I measured

• With the settle row burned, step2 still halts, OB 0x22. The settle fixed nothing.
• step2 halts at 1.024 MHz and above, returns at 500 kHz.
• Half-window 488 ns fails, 1000 ns passes, so the real first-fetch-after-OUT settle is somewhere in 488 ns to 1000 ns.
• Datasheet budget to IR is 382 ns worst case and closes at 488 ns. The missing 100 ns to 600 ns is not in the datasheet path.
• Machine draw on the bench supply ammeter: 1.25 A to 1.34 A at 5 V.

What broke or surprised me

Idle T-states between OUT and the RET fetch do nothing; only a real intervening fetch cures it. So the bottleneck is the RET fetch’s own single T-state, whose setup deadline is the clock edge, and states before it cannot lengthen it. The extra delay is breadboard bus capacitance (100+ pF against the 45 pF a 74LS245 tPD is specced into) plus the REG_A to RAM buffer cross-driver handoff that only an OUT-then-fetch sees. A fetch after a fetch is the same buffer both times, no contention. A driving settle does not help either: OUT cannot know whether the next fetch is ROM or RAM, and a RAM-driving last row makes the ROM case a bus fight.

An earlier note had predicted slower is worse from a transparent-IR-dwell model. The bench said slower is better. That model is retracted, and so is the settle row: it costs a T-state and should be reverted on the next burn.

Zero-burn workaround: never put OUT immediately before RET in RAM code.

Stepping back: every error since the ISA went green has been noise. Ground offsets, a ringing clock stub, a wrong capacitor, a reset wire in the wrong bundle, bus capacitance, and now a transfer that a bump can stop. None of it has been the logic.

Next

The breadboard is at the end of what it can do. Decision: one 2-layer mainboard, the phase E slots as its only connectors, and power designed first. Wrote POWER.md with the record of every power or ground fault chased as logic since 2026-08-24, eight entries, the supply options (old ATX on hand, PicoPSU, plain 5 V brick) and the bench checks that pick between them. Which supply is an open item I have not dug into.