DMA is the last thing left, so now I have to decide
Nothing else on the hardware list
With interrupts, ADC/SBB and SCELBAL running, I don’t think there’s anything left to add to DINO’s core except DMA. I’ve gone back and forth on it for two weeks. On 09-24 it was off the board, the next day it was on hold, and this morning it was back on Rev A as gates plus a connector, with the 8257 itself on a perfboard. Until now there was always something else to do first.
DMA touches 20 pins on 16 chips
I had a feeling it was a big lift, so tonight I counted it from the netlist. No chip has to move and the microcode doesn’t change. The cost is pins: 20 of them on 16 existing chips have to come off their nets and go through a new gate.
| Item | Count |
|---|---|
| New packages on the core | 4 (74HCT74 for HLDA, two 74LS08, one 74LS32) |
| New packages on the perfboard | about 8 or 9, around the 8257 |
| Existing pins rerouted | 20, on 16 chips |
| Microcode change | none |
The rerouted pins are the RAM strobes, the interrupt accept and inject paths, the address bus drivers, the I/O strobes and the decoder enables. The RAM ~WE net is the one the 14 ns write runt was on in September.
DMA goes on the breadboard before the PCB
Rev A as drawn puts the DMA gates in sockets with shunt plugs, so the board can run without them. That isn’t proven either. Even if DMA never gets built, each shunt puts a socket and two more contacts in series on the RAM strobes and the interrupt path. So DMA gets built on the breadboard plus a perfboard first, and Rev A gets whatever works, hardwired.
The module goes next to the MAR board. It’s the only board with the whole address bus and the whole W bus on it, which covers 24 of the roughly 56 signals.
Counting it also showed me that bus mastering has to be designed in from the start. If every bus driver’s enable and every memory strobe had a spare input from day one, this would have cost a few gates.
Open
- Not started. I’m setting DINO down for a bit, and the PCB waits on this.
- Which board U74/U75 physically sit on, and where U81/U82/U84 are now that the interrupt board is split up.
- Which I/O slot the 8257’s registers get, and one shared DMA channel or one per card.
- Whether the HLDA flip-flop clocks off the bus clock or its own gate.