DINO

hardware / status: active

D.I.N.O., Discrete Integrated NISC Operator, is an 8-bit CPU I built from 86 chips on breadboards, 81 of them 74-series, designed in KiCad. Three AT28C64B EEPROMs hold a 24-bit microcode word; program ROM is an AT28C256, RAM a 32K MCM60256. It started as a 25-instruction machine that could add two numbers and has grown, phase by phase, into a 174-instruction ISA with add-with-carry, a 16-bit stack pointer, CALL/RET, interrupts, execute-from-RAM, a 16K memory-mapped I/O window with eight card slots, a 16550 serial card, and a ROM monitor that loads hex over the wire and runs it. It runs SCELBAL, the 1974 BASIC for the 8008, out of the same ROM as the monitor. Most of the hard faults turned out to be analog stuff, not logic. The breadboard is at the end of what it can do at 1.024 MHz. Before the PCB, DMA gets built and tested on the breadboard and a perfboard.

The machine, top-down, 2026-09-10. Microcode and T-state decode on the left, the program counter across the top, RAM, program ROM and the MDR board in the center, registers and the ALU on the right, the LED and DIP switch board at the far right.

Current state

As of 2026-10-06: DINO runs SCELBAL BASIC out of ROM, takes interrupts and does add-with-carry. Everything up through the serial card and the monitor works at 1.024 MHz, and all 32K of RAM works for data and for instruction fetch.

The next hardware is DMA, built on the breadboard and a perfboard before the PCB. That hasn’t started. The mainboard in KiCad is 4 layers with GND and +5V planes, placed but not routed.

Architecture

Horizontal microcode, no pipeline. Each opcode is a table of rows in a 24-bit control word held in three AT28C64B EEPROMs (U9, U15, U23), addressed by opcode and T-state. T0 is the fetch for every opcode, and a 74LS163 T-counter steps the rows until END. The control word is decoded in 3-bit ‘138 banks, so only one source can drive a bus at a time. Every load commits on CLK low, and the RAM write is held off in T-state 0, the one state where the instruction register is transparent. The machine is fully static, so the clock can stop.

Two buses. MDR0-7 is the internal bus (ROM, RAM, registers A/B/C, stack pointer halves, PC halves all drive it through ‘245s). W is the ALU and destination side. A ‘245 bridge (U25) joins them whenever any source is active: MAR and IR latch from W, registers from MDR. The ALU is a pair of 74F382s with ripple carry; all four flags latch in a ‘273 and update only when the ALU is the source.

Interrupts come in on one wire-OR’d ~IRQ line, which the serial card drives through its 7406. The interrupt core (U80-U87) takes the request at an instruction boundary, pushes PC and jumps to a single soft vector at 0x9090 in RAM. Whatever code enables interrupts plants a JMP to its own handler there.

Memory map: ROM at 0x0000-0x3FFF, an I/O window at 0x4000-0x7FFF split into eight 2K card slots, RAM at 0x8000-0xFFFF. The DIP switch is card zero at 0x4000 and the serial card is card one at 0x4800. A new card is a ‘138 on M11-M13 plus whatever chip does the work. Cards only read the address bus; there’s no DMA yet.

ISA: 174 instructions. Immediate and register ALU ops, add and subtract with carry, absolute and memory-indirect loads and stores, conditional branches on C and Z, PUSH/POP, CALL/RET, and OUT to an 8-LED latch. The high nibble of an opcode is its family, so a byte can be disassembled by hand at the bench.

The I/O corner. The last two things to go onto the breadboard: the DIP switch as card zero at 0x4000 and the serial card, a PC16550D with its 3.6864 MHz can and the FTDI breakout, at 0x4800. Both are just memory to the CPU. The stack pointer '169s (U63-U68) sit below them. — The I/O corner. The last two things to go onto the breadboard: the DIP switch as card zero at 0x4000 and the serial card, a PC16550D with its 3.6864 MHz can and the FTDI breakout, at 0x4800. Both are just memory to the CPU. The stack pointer ‘169s (U63-U68) sit below them.

Hardware

86 chips on breadboards: 81 74-series parts (18 ‘245s and 11 ‘373s are most of it), three AT28C64B microcode EEPROMs, an AT28C256 program ROM and an MCM60256 32K SRAM. The serial card adds a 74LS138, a 74LS245, a PC16550D and a 7406N.

Single +5 V rail, drawing 1.25 A to 1.34 A. A 4 MHz can divides down to 1.024 MHz, with a 500 kHz option for timing checks. The UART has its own 3.6864 MHz can and talks to the laptop through an FTDI cable.

Instruments: DSLogic Plus LA (16 channels at 100 MHz in buffer mode), Siglent SDS1204X-E, DMM, TL866 programmer. The ATmega2560 test rig and the FPGA twin are both retired.

Where it started. Dino v0.0.1, schematic dated 2025-06-15: an 8-bit logic sequencer, a 555 timer and a binary counter stepping an EEPROM into an LED bus. One breadboard and a logic analyser.

Software

The ROM monitor takes D, W, O, L and G commands over 9600 8N1, so I can read and write memory, load hex and run it. The interrupt version reads the UART on its receive interrupt into a 16-byte ring and has Ctrl-C. SCELBAL shares the 16K ROM with it. A Python translator turns the 8008 source into DINO code, and its output is checked character for character against the original running on an 8008 emulator. G 0A00 starts it; PEEK, POKE and UDF were patched in. RAM programs load over serial, including a Mandelbrot set that draws 80x33 in 14 seconds.

Everything is generated from the KiCad schematics. A netlist oracle extracts gate equations, microcode_gen.py builds the ROM images with pinned CRCs, and a Python oracle runs the real microcode rows to say what the LEDs should read for every test image.

What the breadboard taught me

Most of the hard faults were ground, a component value or a wire run. When a fault doesn’t care what program is running, I measure GND and VCC on every board before building a logic model. Starring the rails took the worst board from 460 mV of ground offset to 180 mV.
Every external ground enters at the star point. The serial card was grounded through the FTDI for a while, and 250 mA of return current was leaving through the laptop.
Raw CLK doesn’t go on a latch pin at the end of a stub. The stack pointer ‘169s double-clocked until R2 (100R) went in series, and the ALU output latch caught half its next answer until its LE came off a gate.
RESET runs away from CLK and the buses. In the bundle it picked up 1.5 V runts and reset the UART at random.
A component value is copper too. A 1 uF cap where 10 uF belonged gave a 0.8 ms runt instead of a power-on reset.
If I build another one, every bus driver enable and memory strobe gets a spare input from day one, so DMA doesn’t turn into a retrofit.

Open problems

Serial receive drops 1 bits to 0 unless there’s 22 pF on the UART’s A0 pin (U103.28). Why is open.
The PCB power supply is undecided: the old ATX unit, a PicoPSU, or a plain 5 V brick with a supervisor chip.
Never measured: CN+4 after a logic op on the ‘382 (the oracle refuses to guess), bus levels on a healthy machine, and whether run, idle and halt draw differ.
22 instructions and the 15-opcode OUT_ family have never run on silicon. They’re microcode-soft.
23 SETTLE rows cost a T-state each and were added for a fault that turned out to be ground. They come out at the next burn.
Loose ends from bring-up: one halt in the middle of a serial payload on 09-29, seven boards still at 124 mV to 180 mV of ground offset, and why 100 pF on the ALU latch’s LE pin helped.

Build logs

Dated working notes for this project, newest first. Corrections land as new entries.

2026-10-06 DINO DMA is the last thing left, so now I have to decide With interrupts, add-with-carry and BASIC done, DMA is the only hardware left, and counting what it touches moved it to the breadboard before the PCB.
2026-10-06 DINO SCELBAL runs on DINO SCELBAL, the 1974 floating-point BASIC for the 8008, now runs from the ROM socket of a CPU built out of 74-series chips on breadboards, translated instruction by instruction and checked against the original running in an emulator.
2026-10-06 DINO Add-with-carry is one more '157 ADC, SBB, ACI and SBI run on DINO after one 74LS157 on the ALU board, one moved wire and a three-chip microcode burn, and the Mandelbrot program now does 16-bit 8.8 fixed point with them.
2026-10-06 DINO Mandelbrot in 14 seconds, no multiply An 80x33 ASCII Mandelbrot runs from RAM on DINO in 14 s at 1.024 MHz, using one-byte fixed point and tables of squares because the machine has no multiply, no right shift and no add-with-carry.
2026-10-06 DINO Interrupts work, and the monitor has a Ctrl-C Every rung of the interrupt test ladder passes at 1.024 MHz, and a new interrupt-driven monitor, PROG_imon, breaks a running program back to the prompt with Ctrl-C.
2026-10-06 DINO The ALU was latching its own next answer PROG_isa is back to 0xB4 on 35 straight resets after U47, the ALU output latch, got its clock from a spare inverter instead of the raw CLK line.
2026-10-01 DINO Interrupt core wired, and isa now fails on ADD The interrupt hardware is in and the seven lifts are done, but PROG_isa now stops at ADD or SUB instead of reading 0xB4, and so far every new part I’ve probed is clean.
2026-09-29 DINO Most stable DINO yet, and the interrupt microcode is in Same day as the write-runt fix: both peripherals working, RAM programs running, and the interrupt microcode burned with every old instruction still passing.
2026-09-29 DINO The RET that fetched 0xFF was a 14 ns write The RAM-fetch halt is closed: the fetch’s transparent IR let a decoder runt through the write gate, the SRAM got a 14 ns ~WE, and one NOR on T-state 0 fixed it. Rule 30 scrolls out of RAM now.
2026-09-28 DINO A0 at the UART, and a RET that fetches 0xFF The serial receive errors went away with capacitance on U103’s A0 pin, bigxfer made it both ways, and the halt at the end of it turned out to be a RAM fetch of RET that reads 0xFF after some instructions.
2026-09-27 DINO Off the shelf: RESET pickup again, and a UART that reads ones as zeros Interrupts are designed and the chips are on the bench, but the night went to the serial card: a RESET runt was hardware-resetting the 16550 mid-load (twisting the wire with ground stopped it), and received bytes still come back with 1 bits turned to 0.
2026-09-25 DINO Four layers, DMA dropped again, interrupts on a branch The mainboard went to 4 layers with GND and +5V planes, DMA came off the plan for the second time (maybe not for good), and the interrupt microcode is written and host-tested on a branch that has never touched silicon, so DINO is going back on the shelf for a while.
2026-09-14 DINO Mainboard: routed, DRC 0, not the print candidate Four days from a 374x524 mm draft with no tracks to a 299x223 mm 2-layer board with 0 DRC errors: global labels, a power sheet, a 50-pin card bus, annealed placement, Freerouting, GND on two layers. The board still has no bulk caps or measured supply, and two unbuilt additions to carry, so it is not the one that prints. What has to be true before gerbers.
2026-09-10 DINO ISA: 174 opcodes, six addressing modes, what has run The full DINO ISA as it sits in the three microcode EEPROMs: how to read a row, the six addressing modes, every opcode by family, and which ones have actually run on the hardware.
2026-09-08 DINO OUT before a RAM fetch: halts at 1.024 MHz, runs at 500 kHz A staircase of RAM programs pinned a halt to OUT immediately before a fetch from RAM; a microcode settle row was burned and did not fix it; the clock bracket says setup margin, so the next phase is a PCB with power first.
2026-09-07 DINO Monitor L and G commands; RAM 0x8000-0xFFFF proven The monitor gained L (sum-checked hex load) and G (CALL into RAM); dinoload.py types one character per echo; all 32K of RAM is proven for data and fetch.
2025-08-19 DINO Memory module: the SRAM wants an edge on WE 32K ROM and 32K SRAM on a shared address bus behind ‘245s. Level-driven writes failed; a 74LS121 making a 600 ns pulse fixed it. Data pins had been wired backwards.
2025-08-11 DINO Microcode decoder: two AT28C64s and four '138s The control word generator on its own board: IR plus timer state address a pair of EEPROMs, 16 bits out into four ‘138 banks. Verified with DIP switches and a multimeter after a bit-order mistake and several re-burns.
2025-07-31 DINO Program counter: four '193s, worked on first power-up 16-bit PC from four 74LS193s and ‘245s on both sides. Counted and cascaded on the first try. Hand-pushed up/down was too short a pulse for the carry chain; preset failed until a hardwired input transceiver was found.
2025-07-25 DINO 16-bit control word, four decoder banks, sixteen T-states The control word got its shape: four 3-bit ‘138 banks and four direct bits. STA needed eight T-states, so the ring went to sixteen with a second ‘138 and no reset gate.
2025-07-19 DINO Six-state ring counter on the LA ‘163 + ‘138 + ‘00 + the 555 from the sequencer. Six one-hot states at about 60 ms each on the logic analyser, then a memory map and IR sketch that mostly didn’t survive.
2025-07-18 DINO Control unit: SAP-1 timing, control words in an EEPROM Two days with Malvino and no soldering. SAP-1’s T0-T5 timing, a ring counter out of a ‘163 and a ‘138, and the decision to put the control words in an EEPROM instead of gates.
2025-07-16 DINO v0.0.1: 555-clocked LED sequencer, no control unit DINO v0.0.1 was a 555-clocked LED sequencer with a 32K SRAM. It worked until three things shared the bus, and that’s when I found out I didn’t have a control unit.