The spare board gets a new USB port, and slot 4 stops being hardcoded
What I tried
DP051FY9 came back from the fab with a wobbly USB micro connector. It was shaky from the first day and it finally came off the board completely while I was plugging and unplugging it. I cleaned the old solder off to see what was actually left under there.
I remounted a new USB micro on a hot plate. Then I went around the shell tabs with an iron and globbed solder on until the ground felt solid. It is ugly. After that I put epoxy anywhere I could get it to grab the PCB, staying away from anything that would run into the connector opening.
With the board alive again I wanted both cards in the machine at the same time, which meant the second one had to live somewhere other than slot 4. That turned into a much bigger software job than the repair.
What I measured
Both boards enumerate over USB. A JTAG scan returns idcode 0x41113043, LFE5U-85, on each of them.
SDMTEST passes all 1024 banks on both cards, DP0517RX in slot 4 and DP051FY9 in slot 2, with both seated at once. PR#4 and PR#2 each bring up the 8008 glass terminal, and both cards read and write 8008 RAM. The obscurus $C800 monitor also comes up on both, one arming through $C0C7 and the other through $C0A7, and R, W, B and D work on each.
Rebuilding everything at SLOT=4 after the sweep gives byte-identical output to before it. That is 12 SDM binaries, b8fw.bin, slot_rom.bin and monitor.bin. The A8 acceptance gate still comes out byte-identical to its reference.
At SLOT=2 the differences are only what they should be. FARM.bin differs from the slot 4 build in 56 bytes and all 56 are a $C0Cx operand becoming $C0Ax. CPBOOT is 20 bytes. SDMTEST is 14. The b8008 slot ROM differs in 9 bytes, 3 of them the high byte of an internal jump and 6 register operands.
The b8008 slot ROM uses 122 bytes of its 256.
What broke or surprised me
One and a half of the five ground pads lifted with the old connector, so I was down to three and a half.
b8008_hamr had not been buildable since 2026-07-10. Moving the netlist to build-time FuseSoC generation changed a port. The old vendored core took int_vector, 3 bits, a vector number, and built the instruction itself as {2’b00, int_vector} and then {that, 3’b101}. The generated core takes int_instruction, 8 bits, already encoded. b8008_hamr_top.v was last touched 2026-07-07 and still handed it int_vector, so synthesis stopped there.
The card was fine the whole time. It kept running the bitstream I flashed on 07-08, before the migration. I just had no reason to rebuild that design for 66 days, so I never saw it fail. The fix at the top level is {2’b00, cpu_int_vec, 3’b101}, the same bits the old core computed internally. An 8008 RST n encodes as 00 nnn 101.
What the build system did do is make the failure present in the wrong place. Yosys prints ERROR, make carries on and prints “Synthesis complete”, then prints “Place and route complete”, then fails three steps later at ecppack with a missing input file. That cost me time today.
signal_check was driving DATA_OE off nI_O_STROBE. Every slot sees that signal, so with two cards seated both would have driven the data bus on any $C800 access. block_hamr already carries a comment about hitting this in April, serving $FF at $C800 and breaking the 80 column firmware and the BASIC.SYSTEM hooks. signal_check is from bring-up week and never got the fix.
The coprocessor programs were the interesting part. They PUT SDRAMLIB, which already had a SLOT equate, and then declared the coprocessor ports at $C0C9 through $C0CD as literals. Adding a slot knob and stopping there would have built a binary that talks SDRAM to slot 2 and coprocessor to slot 4, which is to say to the other card, silently.
Four programs PUT both SDRAMLIB and CPLIB, so neither library could own the SLOT equate without colliding. It went into SLOTDEF.S with SLOTBASE, and 14 top level sources PUT that first. About 95 literals across 19 sources in the end.
The slot ROMs cannot patch themselves at startup. The ROM is an initial $readmemh with one combinational read and no write port, so the usual trick of fixing up operands at runtime is not available in there. They get reassembled per slot instead, with the ORG derived from the same knob.
Next
The build needs a real gate on the synthesis step. A yosys ERROR should stop make there instead of carrying on to print two success lines and failing at ecppack.
The slot ROMs are still not position independent, so moving a card between slots means a rebuild and a reflash.
Next board revision gets a through hole USB connector. The SMD part puts all the mechanical load into the pads and the shell tabs, and a connector you plug and unplug is going to lose that fight eventually.