Logic analyzer proof of concept: live captures on HIRES with marker deltas that match the signal
What I tried
The whole pipeline: probes into the FPGA, samples written to SDRAM at 1 MHz, a trigger that arms, waits and snaps on the configured edge, decimated data read back over the bus, and 6502 code drawing 8 channels on HIRES. The 80-column text area at the bottom shows cursor position, A and B markers with their delta, trigger config and the zoom preset. Four zoom windows: 38 us, 88 us, 133 us and 266 us. The cursor moves pixel by pixel with a time readout in microseconds. Sample rate came in at 1 MHz, down from the 2 MHz I planned in January.






What I measured
- Six of eight channels populated: 500 kHz, 125 kHz and 62.5 kHz signals, each with its inverted complement on a separate channel.
- Two markers dropped on a signal give a delta that matches the signal’s actual period.
- The timing agrees with what the bench scope shows.
What broke or surprised me
It is a proof of concept with rough edges. There is no paging through the capture buffer; the data is in SDRAM but the display cannot scroll to it. There is no continuous or roll mode. The button debounce capture I wanted as the demo is in the buffer but needs deeper zoom and paging to see. Precision is not lab grade. I am not chasing these now.
Next
Fuji Hamr: FujiNet-compatible storage on the same card, which means emulating a Liron card. Same PCB, same SDRAM, same bus interface, different gateware.