A Liron card written from the IWM spec boots ProDOS from FujiNet on the first flash

What I tried

The old smart_hamr had reached the point of booting ProDOS from a FujiNet, but it got there on a stack of tuning: a 700 us DRAIN_DELAY holdoff on the handshake register (5012 fclk, up from 200 us on 04-29), a read-state flush on Q6 falling, a buffer pre-seed on Q7 rising, an sp_drive_gate that forced ENBL inactive in SmartPort mode, and a write bit cell of 27 fclk where the spec says 28. None of it was in a document. I started over with one rule: every constant comes from the IWM Specification rev 19, US patent 4,742,448, the SmartPort bus spec, or the Liron schematic 670-9107, and there are no tuning knobs.

iwm_asic.v is the result, one FCLK domain. Phase 0 is scaffolding with the verbatim Liron ROM. Phase 1 is the state and mode registers, the data-out mux and the ENBL timer. Phase 2 is the write path: writeShifter, bit timer and counter, underrun, write request, with the spec’s 28/32/14/16 bit-cell constants and the midpoint toggle at bitCell»1. Phase 3 is the read path: 2-FF rddata sample, latch-mode framing that syncs on the first $FF then takes 8 bits per byte, GCR fallback, and the x7 clear timer from column 8 of the patent. Phase 4 is a full ProDOS session. All of it was written and building clean on 05-02, waiting for a flash.

What I measured

• 05-03, first flash: ProDOS boots from FujiNet.
• Full SmartPort enumeration, ten devices, unit numbers 0x81 through 0x8a.
• READ_BLOCK, STATUS and CONTROL all work.
• Phases 0 to 4 marked PASS the same day.

What broke or surprised me

I expected it to fail without the hacks. It did not, which means none of them were load-bearing for the Liron protocol. They were all working around something else.

Part of that something else showed up the same day. The FujiNet log filled with data_chksum=1 and Send REQ timeout dest=0x83, which reads like a bit-cell timing fault in the emulation. It was the ESP32’s own debug printf flooding its serial port and stalling the ISR that samples the IWM line. Turning the print rate down dropped the error rate. Any FujiNet-side error now gets checked against the ESP32 debug level before I touch the gateware.

Next

Phase 5: second drive, WRITE_BLOCK and FORMAT. I never started it. Read-only SmartPort from FujiNet was what I needed, and the SDRAM monitor work pulled me off.