Apple IIeAztec C 3.2b on one 800K diskMerged the eight Aztec C65 floppies onto one bootable 800K image, hit the shell’s reload bug, wrote a 186-byte loader around it, compiled hello world, and decided C isn’t worth it on this machine.
DINOThe instruction set, all 174 of themThe full DINO ISA as it sits in the three microcode EEPROMs: how to read a row, the six addressing modes, every opcode by family, and which ones have actually run on the hardware.
SigScopeFront panel, scope-style trigger, and persistenceRebuilt the UI as knobs and lit buttons laid out like the scope, fixed the trigger workflow and the Auto Setup slowdown, then added phosphor-style persistence that also drives the scope’s own persistence.
Why this site existsA static build log for Byte Hamr Labs projects, and the rules it follows.
DINOOUT before a RAM fetch halts; the breadboard is doneA staircase of RAM programs pinned a halt to OUT immediately before a fetch from RAM; a microcode settle row was burned and did not fix it; the clock bracket says setup margin, so the next phase is a PCB with power first.
IBM 5160 and 3270 PC bring-upTandon alignmentOne of the two Tandon TM100-2 drives was off track. Scope on the test points, a DEBUG loop to hold the head, and a cam adjustment fixed it.
IBM 5160 and 3270 PC bring-upA dead ST-251First hard drive attempt on the 5271 came up at about 21 MB, then never finished a format, and the drive turned out to be dead.
Byte HamrAn Intel 8008 in the card, and a whole 8008 toolchain that lives on the Apple IIeThe b8008 core from my 8008 VHDL project went into the ECP5 with a PR#4 glass terminal; over two days the IIe gained a loader, a byte-compare gate, a native 8008 assembler, and an 80-column editor with the assembler built in, all checked against the ASL reference object.
Intel 8008 VHDLThe monitor finally talks, and the flaky boot was the level shiftersMonths of address-dependent corruption came down to TXS0108E shifters run past absolute maximum, a bootstrap FSM on the wrong clock, and my own backspace keystrokes. ROM goes back inside the FPGA, firmware reflash drops from 4 minutes to 0.7 seconds, and 42 of 42 ISA self-tests pass on silicon.
Intel 8008 VHDLOne clock: phi1 and phi2 become enables, then a PLLSix phases of refactor take every flop off the derived phi clocks and onto one master clock, the gated debug clock becomes a hold signal, and a PLL brings the system to 25 MHz where timing closes without multicycle constraints.
Byte HamrRev 2 boards arrive and both pass bring-upTwo Rev 2 boards enumerated over USB on arrival; the gateware tree split into rev1 and rev2, signal_check was ported, and the walking-ones loopback through the data transceiver passed on both boards.
Byte HamrBlock Hamr: a ProDOS block device that survives a power cycleDropped the SmartPort protocol stack for an eight-register block interface, got SAVE and CREATE and nested directories working to SDRAM, then added write-through flash persistence and 12 MB volumes over four days.
Intel 8008 VHDLFirst b8008 silicon, and Yosys eats the ROMb8008 validated on the ECP5-5G on 2026-01-02, a UART echo and a monitor with H and D commands by the 7th, and a Yosys ROM initialization bug that corrupts contents when the fill is 0xFF.
Intel 8008 VHDLTwo 8008s that ran and got thrown outs8008 reached hardware with the wrong timing model, v8008 drowned in conditionals, and b8008 starts from a clean slate with one module per block-diagram box.
DINOMemory module: the SRAM wants an edge on WE32K ROM and 32K SRAM on a shared address bus behind ‘245s. Level-driven writes failed; a 74LS121 making a 600 ns pulse fixed it. Data pins had been wired backwards.
DINOMicrocode decoder: two AT28C64s and four '138sThe control word generator on its own board: IR plus timer state address a pair of EEPROMs, 16 bits out into four ‘138 banks. Verified with DIP switches and a multimeter after a bit-order mistake and several re-burns.
DINOProgram counter: four '193s, worked on first power-up16-bit PC from four 74LS193s and ‘245s on both sides. Counted and cascaded on the first try. Hand-pushed up/down was too short a pulse for the carry chain; preset failed until a hardwired input transceiver was found.
DINOSix-state ring counter on the LA‘163 + ‘138 + ‘00 + the 555 from the sequencer. Six one-hot states at about 60 ms each on the logic analyser, then a memory map and IR sketch that mostly didn’t survive.
DINOThe control unit, on a notebook pageTwo days with Malvino and no soldering. SAP-1’s T0-T5 timing, a ring counter out of a ‘163 and a ‘138, and the decision to put the control words in an EEPROM instead of gates.
DINOThe sequencer that wasn't a computerDINO v0.0.1 was a 555-clocked LED sequencer with a 32K SRAM. It worked until three things shared the bus, and that’s when I found out I didn’t have a control unit.