IBM 5160 and 3270 PC bring-upKermit, the 387 and 256 KB of Inboard RAMThe 5271 moves files to the Mac over Kermit at 115200, its A80387DX-25 passes Intel’s diagnostic, and a driver-free RAM test and Intel’s iNBRDPC.SYS both find 256 KB of extended memory with nothing bad. It has Turbo C 2.0, Turbo Debugger and MASM 6.00 on it now.
UniDisk 3.5 controllerDisk Hamr: printed, fitted, orderedA flat-bottomed print of the second layout goes into the case with the mechanism and the DB-19, the Gerbers go to PCBWay, the parts list goes to DigiKey with one substitution and the LED resistor read off the original board, and the assembly plan settles on a hot plate for everything but the Pico.
UniDisk 3.5 controllerDisk Hamr: laid out again, by hand this timeWriting the bill of materials and checking the board against it, then a 3D print that put the mechanism header 11 mm off, sent the layout back for a second pass: placed by hand, re-routed with Freerouting, +5 as 1 mm traces instead of a pour, +12 on the back, the tab headers matching the original, and the original’s LED circuit traced.
UniDisk 3.5 controllerDisk Hamr: the PCB is routedThe controller board is placed, routed and DRC clean: hand-routed once through an MCP bridge, then redone by Freerouting from a clean field and fixed up by hand, with +5 and ground pours, a +12 band, a name and a hammer on the silk, and a STEP out for the case fit.
UniDisk 3.5 controllerM8-M9: the daisy chain, once 5V reached the second driveMy board and the working UniDisk share the Liron card in either order, a full 800K disk copied from my drive to the UniDisk boots, the whole rig runs off the IIe after a thin jumper had starved the UniDisk to 4.3 V, and disk swaps, write-protect, ejects and resets all behave like the original.
UniDisk 3.5 controllerM2-M3: the whole disk, once 5V got thereThe Pico reads a full 800K ProDOS disk byte-identical to its source image, on both test-bed mechanisms, in about 2 minutes. Most of the afternoon went to a read chain that looked dead and was actually starved: the drive’s +5V was sagging to 4.0 V through breadboard wiring.
UniDisk 3.5 controllerM1: the mechanism answersThe Pico reads all 16 status bits off the Sony mechanism over a USB console, and the drive identifies as an 800K double-sided unit on the first try. RD settles 27-35 ns after an address change, and a motor that kept spinning after a timeout got fixed before the first flash.
UniDisk 3.5 controllerM0: the strobe on every power edgeThe Pico 2 and two shifter boards are wired to a dead drive’s mechanism and the bring-up firmware is flashed. A reset is clean, but every Pico power edge pushes a 5 V LSTRB strobe at the mechanism, which only ignores it because /ENBL stays high.
Vim 5.8 for the IBM XTVim on the 5160, and the int 22h refusalVim 5.8 built with Open Watcom runs on the real 5160 and swaps itself out for :!, after a fix for a vector check that only real hardware tripped. The fork is public at github.com/robertrico/vim-xt.
UniDisk 3.5 controllerGoing around the CXD1013I’m replacing the UniDisk 3.5 controller with an RP2350 that drives the Sony 800K mechanism directly, the Apple 800K drive spec makes that possible, and the two cable breakouts are built and beep-checked.
DINOSCELBAL runs on DINOSCELBAL, the 1974 floating-point BASIC for the 8008, now runs from the ROM socket of a CPU built out of 74-series chips on breadboards, translated instruction by instruction and checked against the original running in an emulator.
DINOAdd-with-carry is one more '157ADC, SBB, ACI and SBI run on DINO after one 74LS157 on the ALU board, one moved wire and a three-chip microcode burn, and the Mandelbrot program now does 16-bit 8.8 fixed point with them.
DINOMandelbrot in 14 seconds, no multiplyAn 80x33 ASCII Mandelbrot runs from RAM on DINO in 14 s at 1.024 MHz, using one-byte fixed point and tables of squares because the machine has no multiply, no right shift and no add-with-carry.
DINOInterrupts work, and the monitor has a Ctrl-CEvery rung of the interrupt test ladder passes at 1.024 MHz, and a new interrupt-driven monitor, PROG_imon, breaks a running program back to the prompt with Ctrl-C.
DINOThe ALU was latching its own next answerPROG_isa is back to 0xB4 on 35 straight resets after U47, the ALU output latch, got its clock from a spare inverter instead of the raw CLK line.
DINOInterrupt core wired, and isa now fails on ADDThe interrupt hardware is in and the seven lifts are done, but PROG_isa now stops at ADD or SUB instead of reading 0xB4, and so far every new part I’ve probed is clean.
DINOThe RET that fetched 0xFF was a 14 ns writeThe RAM-fetch halt is closed: the fetch’s transparent IR let a decoder runt through the write gate, the SRAM got a 14 ns ~WE, and one NOR on T-state 0 fixed it. Rule 30 scrolls out of RAM now.
DINOA0 at the UART, and a RET that fetches 0xFFThe serial receive errors went away with capacitance on U103’s A0 pin, bigxfer made it both ways, and the halt at the end of it turned out to be a RAM fetch of RET that reads 0xFF after some instructions.
DINOOff the shelf: RESET pickup again, and a UART that reads ones as zerosInterrupts are designed and the chips are on the bench, but the night went to the serial card: a RESET runt was hardware-resetting the 16550 mid-load (twisting the wire with ground stopped it), and received bytes still come back with 1 bits turned to 0.
DINOFour layers, DMA dropped again, interrupts on a branchThe mainboard went to 4 layers with GND and +5V planes, DMA came off the plan for the second time (maybe not for good), and the interrupt microcode is written and host-tested on a branch that has never touched silicon, so DINO is going back on the shelf for a while.
Tandy CoCo 3Pulling a 32 MHz clock mod out of a CoCo 3The flaky 6309 CoCo 3 boots and survives tapping after an undocumented 32 MHz clock mod came out, the oscillator went back to what the schematic calls for, and the corroded GIME socket got cleaned.
IBM 5160 and 3270 PC bring-upXT-IDE rev 4 and a 32 MB CFA 32 MB CF card works as D: on the 5160 with an XT-IDE rev 4 and XTIDE Universal BIOS r638. In the 5271 the same card’s option ROM only runs once the machine is warm, and freezes when it does.
DINOMainboard: routed, DRC 0, not the print candidateFour days from a 374x524 mm draft with no tracks to a 299x223 mm 2-layer board with 0 DRC errors: global labels, a power sheet, a 50-pin card bus, annealed placement, Freerouting, GND on two layers. The board still has no bulk caps or measured supply, and two unbuilt additions to carry, so it is not the one that prints. What has to be true before gerbers.
Apple IIeAztec C 3.2b on one 800K diskMerged the eight Aztec C65 floppies onto one bootable 800K image, hit the shell’s reload bug, wrote a 186-byte loader around it, compiled hello world, and decided C isn’t worth it on this machine.
DINOISA: 174 opcodes, six addressing modes, what has runThe full DINO ISA as it sits in the three microcode EEPROMs: how to read a row, the six addressing modes, every opcode by family, and which ones have actually run on the hardware.
SigScopeFront panel, scope-style trigger, and persistenceRebuilt the UI as knobs and lit buttons laid out like the scope, fixed the trigger workflow and the Auto Setup slowdown, then added phosphor-style persistence that also drives the scope’s own persistence.
Why this site existsA static build log for Byte Hamr Labs projects, and the rules it follows.
DINOOUT before a RAM fetch: halts at 1.024 MHz, runs at 500 kHzA staircase of RAM programs pinned a halt to OUT immediately before a fetch from RAM; a microcode settle row was burned and did not fix it; the clock bracket says setup margin, so the next phase is a PCB with power first.
IBM 5160 and 3270 PC bring-upTandon alignmentOne of the two Tandon TM100-2 drives was off track. Scope on the test points, a DEBUG loop to hold the head, and a cam adjustment fixed it.
IBM 5160 and 3270 PC bring-upA dead ST-251First hard drive attempt on the 5271 came up at about 21 MB, then never finished a format, and the drive turned out to be dead.
Byte HamrAn Intel 8008 in the card, and a whole 8008 toolchain that lives on the Apple IIeThe b8008 core from my 8008 VHDL project went into the ECP5 with a PR#4 glass terminal; over two days the IIe gained a loader, a byte-compare gate, a native 8008 assembler, and an 80-column editor with the assembler built in, all checked against the ASL reference object.
Intel 8008 VHDLThe monitor finally talks, and the flaky boot was the level shiftersMonths of address-dependent corruption came down to TXS0108E shifters run past absolute maximum, a bootstrap FSM on the wrong clock, and my own backspace keystrokes. ROM goes back inside the FPGA, firmware reflash drops from 4 minutes to 0.7 seconds, and 42 of 42 ISA self-tests pass on silicon.
Intel 8008 VHDLOne clock: phi1 and phi2 become enables, then a PLLSix phases of refactor take every flop off the derived phi clocks and onto one master clock, the gated debug clock becomes a hold signal, and a PLL brings the system to 25 MHz where timing closes without multicycle constraints.
Byte HamrRev 2 boards arrive and both pass bring-upTwo Rev 2 boards enumerated over USB on arrival; the gateware tree split into rev1 and rev2, signal_check was ported, and the walking-ones loopback through the data transceiver passed on both boards.
Byte HamrBlock Hamr: a ProDOS block device that survives a power cycleDropped the SmartPort protocol stack for an eight-register block interface, got SAVE and CREATE and nested directories working to SDRAM, then added write-through flash persistence and 12 MB volumes over four days.
Intel 8008 VHDLFirst b8008 silicon, and Yosys eats the ROMb8008 validated on the ECP5-5G on 2026-01-02, a UART echo and a monitor with H and D commands by the 7th, and a Yosys ROM initialization bug that corrupts contents when the fill is 0xFF.
Intel 8008 VHDLTwo 8008s that ran and got thrown outs8008 reached hardware with the wrong timing model, v8008 drowned in conditionals, and b8008 starts from a clean slate with one module per block-diagram box.
DINOMemory module: the SRAM wants an edge on WE32K ROM and 32K SRAM on a shared address bus behind ‘245s. Level-driven writes failed; a 74LS121 making a 600 ns pulse fixed it. Data pins had been wired backwards.
DINOMicrocode decoder: two AT28C64s and four '138sThe control word generator on its own board: IR plus timer state address a pair of EEPROMs, 16 bits out into four ‘138 banks. Verified with DIP switches and a multimeter after a bit-order mistake and several re-burns.
DINOProgram counter: four '193s, worked on first power-up16-bit PC from four 74LS193s and ‘245s on both sides. Counted and cascaded on the first try. Hand-pushed up/down was too short a pulse for the carry chain; preset failed until a hardwired input transceiver was found.
DINOSix-state ring counter on the LA‘163 + ‘138 + ‘00 + the 555 from the sequencer. Six one-hot states at about 60 ms each on the logic analyser, then a memory map and IR sketch that mostly didn’t survive.
DINOControl unit: SAP-1 timing, control words in an EEPROMTwo days with Malvino and no soldering. SAP-1’s T0-T5 timing, a ring counter out of a ‘163 and a ‘138, and the decision to put the control words in an EEPROM instead of gates.
DINOv0.0.1: 555-clocked LED sequencer, no control unitDINO v0.0.1 was a 555-clocked LED sequencer with a 32K SRAM. It worked until three things shared the bus, and that’s when I found out I didn’t have a control unit.